Research at AEIM
We conduct research in flip-chip packaging, focusing on advanced interconnect design, assembly processes, material optimization, and reliability analysis for high-performance electronic systems.
Our processes ensure that the pad gap is maintained at less than 200 microns. This careful control allows the to expand and contract effectively during thermal expansion, promoting optimal performance and reliability in our applications.
Precise alignment is crucial for high repeat and product reliability. By implementing advanced techniques, we ensure consistent accuracy in our processes. Choose us for dependable results every time.
Our Expertise
Advanced Flip-Chip Packaging and Precision Interconnect Assembly
Our research focuses on high-precision flip-chip packaging and heterogeneous integration for next-generation microelectronic systems. We develop and evaluate chip-to-substrate interconnect technologies with placement accuracy down to ±3 µm, enabling fine-pitch assembly for compact, high-density semiconductor packages.
Our packaging work includes the fabrication and characterization of micro-bump and solder bump interconnects, underfill-assisted assembly, and thermomechanical reliability evaluation. We investigate interconnect pitch scaling, alignment tolerance, bonding pressure, reflow behavior, underfill flow, and interface integrity to improve package yield and long-term device reliability.
Key technical capabilities include:
Flip-chip placement accuracy: up to ±3 µm
Fine-pitch interconnect assembly: down to 20–50 µm pitch
Micro-bump diameter range: approximately 10–30 µm
Die-to-substrate integration: silicon, glass, ceramic, and organic substrates
Reliability testing: thermal cycling, shear testing, cross-section analysis, and failure inspection
Research focus: electromigration, interfacial adhesion, underfill reliability, thermal stress, and high-density heterogeneous integration
This research supports advanced packaging solutions for AI accelerators, high-performance computing, RF and 5G/6G systems, automotive electronics, MEMS devices, and advanced sensor platforms.
Non-Contact Lift-and-Place Technology
Our technology is built around non-contact lifting, handling, and precision placement of delicate semiconductor components for advanced packaging, flip-chip assembly, heterogeneous integration, MEMS, sensors, and optoelectronic devices.
Unlike conventional vacuum pick-up or mechanical gripping, our non-contact lift-and-place approach minimizes direct interaction with the device surface. This reduces mechanical stress, particle contamination, surface defects, triboelectric charge generation, and electrostatic discharge risk, helping preserve device integrity throughout the assembly process.
By avoiding physical contact during component handling, the system helps suppress triboelectric charging caused by material-to-material contact and separation. This is critical for sensitive semiconductor devices, where electrostatic energy and localized electric-field buildup can create latent defects, degrade thin-film structures, damage fine-pitch interconnects, and reduce long-term product lifetime.
Technical Capability Highlights
Placement accuracy: up to ±3 µm
Repeatability: better than ±1–2 µm under controlled process conditions
Non-contact handling gap: typically 50–300 µm, depending on die size and material
Compatible die thickness: down to 50 µm ultra-thin dies
Component size range: from sub-millimeter chips to large-area dies
Surface contact force: approximately 0 N during lift and transfer
ESD risk reduction: minimized through suppression of triboelectric charge accumulation
Process advantage: reduced surface contamination, reduced die chipping, lower mechanical stress, and improved assembly yield